Influence of VIA stacking for high density of consumer electronics products

The multistage stacked VIA technology is one of the key technologies for the achievement of high-density packaging, but it appears that the influence of VIA stacking is not sufficiently well understood. The influence of one- to five-level VIA stacking technologies is studied with respect to the parameters of stress and strain from the viewpoint of reliability, comparing the conditions in which these VIAs are located directly on the RFP [Resin Filled PTH (Pin Through Hole)], and the condition in which they are located to the left and right at some distance from the RFP. The maximum stress occurs at the smallest VIA neck, and it is recommended that VIA stacking be designed at some distance from the RFP. Guidelines for optimized design of substrates that have stacked VIAs are provided. © 2010 Wiley Periodicals, Inc. Electron Comm Jpn, 93(11): 1–7, 2010; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10320