Probabilistic design of integrated circuits with correlated input parameters

This paper presents an application of advanced first-order second-moment (AFOSM) reliability method to probabilistic design of integrated circuits with correlated parameters. The method avoids the transformation to the space of uncorrelated parameters and provides a conservative estimate of the yield. Optimal nominal values are found such that the cost of tolerances is minimized while the desired yield is achieved. Numerical results are presented for a switched capacitor filter and verified by Monte Carlo simulation.

[1]  G. Hachtel The simplicial approximation approach to design centering , 1977 .

[2]  K. Singhal,et al.  Statistical design centering and tolerancing using parametric sampling , 1981 .

[3]  M. A. Styblinski,et al.  Yield and variability optimization of integrated circuits , 1995 .

[4]  G. E. Muller Limit parameters: the general solution of the worst-case problem for the linearized case (IC design) , 1990, IEEE International Symposium on Circuits and Systems.

[5]  Ping Yang,et al.  Parametric yield optimization for MOS circuit blocks , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Stephen W. Director,et al.  A new methodology for the design centering of IC fabrication processes , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  John W. Bandler,et al.  Efficient quadratic approximation for statistical design , 1989 .

[8]  K. Krishna,et al.  Optimization Of Parametric Yield: A Tutorial , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[9]  John W. Bandler,et al.  Circuit optimization: the state of the art , 1988 .

[10]  J. Mavor,et al.  Exact design of stray-insensitive switched-capacitor LDI ladder filters from unit element prototypes , 1986 .

[11]  J. Vlach,et al.  Design for nonsymmetrical statistical distributions , 1997 .

[12]  Kumaraswamy Ponnambalam,et al.  A unified approach to statistical design centering of integrated circuits with correlated parameters , 1999 .

[13]  Stephen W. Director,et al.  The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Kurt Antreich,et al.  Circuit analysis and optimization driven by worst-case distances , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Sung-Mo Kang,et al.  Worst-case analysis and optimization of VLSI circuit performances , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Peter Feldmann,et al.  OPTIMIZATION OF PARAMETRIC YIELD: A TUTORIAL , 1992 .

[17]  Jirí Vlach,et al.  Ellipsoidal method for design centering and yield estimation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..