A 12-bit, 1 MS/s SAR-ADC for a CZT-based multi-channel gamma-ray imager using a new digital calibration method

The successive approximation register-analog to digital converter (SAR-ADC) is widely used in the CdZnTe-based gamma-ray imager because of its outstanding characteristics of low power consumption, relatively high resolution, and small die size. This study proposes a digital bit-by-bit calibration method using an input ramp signal to further improve the conversion precision and power consumption of an SAR-ADC. The proposed method is based on the sub-radix-2 redundant architecture and the perturbation technique. The proposed calibration algorithm is simpler, more stable, and faster than traditional approaches. The prototype chip of the 12-bit, 1 MS/s radiation-hardened SAR-ADC has been designed and fabricated using the TSMC 0.35 μm 2P4M CMOS process. This SAR-ADC consumes 3 mW power and occupies a core area of 856× 802μm2. The digital bit-by-bit calibration algorithm is implemented via MATLAB for testing flexibility. The effective number of bits for this digitally calibrated SAR-ADC reaches 11.77 bits. The converter exhibits high conversion precision, low power consumption, and radiation-hardened design. Therefore, this SAR-ADC is suitable for multi-channel gamma-ray imager applications.

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