On the Origin of Thermal Runaway in a Trench Power MOSFET

In this paper, we investigate the origin of thermal runaway in the trench power MOSFET of a modern smart power IC technology. Experimental data on the temperature rise during power pulses show that the onset of thermal runaway depends on the biasing condition even if the power pulses have equal power dissipation. The beginning of thermal runaway in this work is denoted by the inflection point in the measured temperature data. For the experimental data points, the onset varies from 340 °C to 520 °C. Comparison of these experimental data with an analysis based on the stability factor shows very good agreement. The stability factor analysis demonstrates that, above the temperature compensation point (TCP), the driving force for thermal runaway is the thermally generated leakage current of the parasitic n-p-n bipolar transistor. The decrease of mobility and, hence, the MOS channel current above the TCP stabilizes the power MOSFET. In contrast, below the TCP, both the increase of the MOS channel current and the parasitic n-p-n bipolar transistor leakage current with temperature contribute to the thermal runaway.

[1]  J Gowar,et al.  Power MOSFETs: Theory and Applications , 1989 .

[2]  P. D. Maycock,et al.  Thermal Conductivity of Silicon from 300 to 1400°K , 1963 .

[3]  M. Stecher,et al.  Influence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[4]  M. Stecher,et al.  Power-cycling of DMOS-switches triggers thermo-mechanical failure mechanisms , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[5]  M. Glavanovics,et al.  Impact of thermal overload operation on wirebond and metallization reliability in smart power devices , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[6]  K. Mckay Avalanche Breakdown in Silicon , 1954 .

[7]  Martin Pfost,et al.  Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures , 2008, 2008 20th International Symposium on Power Semiconductor Devices and IC's.

[8]  H. Grubin The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[9]  Stefan Decker,et al.  Fabrication of trench isolation and trench power MOSFETs in a smart power IC Technology with a single trench unit process , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[10]  Taylor R. Efland,et al.  Avalanche-induced thermal instability in Ldmos transistors , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[11]  Matthias Stecher,et al.  A TLP-based characterization method for transient gate biasing of MOS devices in high-voltage technologies , 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

[12]  K. Shenai,et al.  Electrothermal effects during unclamped inductive switching (UIS) of power MOSFET's , 1997 .

[13]  Matthias Stecher,et al.  Scaling of temperature sensors for smart power MOSFETs , 2008 .

[14]  H. K. Gummel A charge control relation for bipolar transistors , 1970, Bell Syst. Tech. J..

[15]  C. R. Crowell,et al.  Temperature dependence of avalanche multiplication in semiconductors , 1966 .

[16]  Giorgio Baccarani,et al.  An Analytical, Temperature-dependent Model for Majority- and Minority-carrier Mobility in Silicon Devices , 2000, VLSI Design.

[17]  Philip L. Hower Safe operating area - a new frontier in Ldmos design , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[18]  J. C. Jaeger,et al.  Conduction of Heat in Solids , 1952 .

[19]  V. d'Alessandro,et al.  Analytical model for thermal instability of low voltage power MOS and SOA in pulse operation , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[20]  P. L. Hower,et al.  Comparison of one- and two-dimensional models of transistor thermal instability , 1974 .

[21]  M. Tack,et al.  XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit , 2006, 2006 International Electron Devices Meeting.

[22]  A. Consoli,et al.  Thermal instability of low voltage power-MOSFETs , 1999, 30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321).

[23]  T. Dyer,et al.  Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[24]  R. A. Logan,et al.  Ionization Rates of Holes and Electrons in Silicon , 1964 .