Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication

A selectively-adaptive and configurable 8-72 tap distributed arithmetic FIR filter consuming 0.016mm2 total area in 22nm CMOS with a companion RLS-based adaptation hardware accelerator for large scale signal processing in communication systems is presented. Overhead of duplicate LUTs in partial-parallel implementations is avoided by using multi-port memories to achieve required application throughputs and memory footprint is optimally reduced by systematically trading logic for memory. The first SoC implementation of a serialized RLS-based adaptation hardware accelerator that adapts the filter coefficients on an as-needed basis consumes 0.089mm2 total area at an estimated total power of 12.5mW at 0.8V supply.

[1]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.

[2]  Rui Guo,et al.  Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[4]  Dejan Markovic,et al.  A 1–190MSample/s 8–64 tap energy-efficient reconfigurable FIR filter for multi-mode wireless communication , 2010, 2010 Symposium on VLSI Circuits.

[5]  S.A. White,et al.  Applications of distributed arithmetic to digital signal processing: a tutorial review , 1989, IEEE ASSP Magazine.

[6]  Douglas L. Jones.  Efficient computation of time-varying and adaptive filters , 1993, IEEE Trans. Signal Process..

[7]  Basant K. Mohanty,et al.  A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm , 2013, IEEE Transactions on Signal Processing.

[8]  Venkatesh Krishnan,et al.  LMS adaptive filters using distributed arithmetic for high throughput , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Rafi Ahamed Shaik,et al.  Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Sang Yoon Park,et al.  Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  B. Nikolic,et al.  Power-Performance Optimal DSP Architectures and ASIC Implementation , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[12]  Peter Zipf,et al.  Reconfigurable FIR filter using distributed arithmetic on FPGAs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[13]  David V. Anderson,et al.  Adaptive filters using modified sliding-block distributed arithmetic with offset binary coding , 2009, 2009 IEEE International Conference on Acoustics, Speech and Signal Processing.