Performance analysis of network-on-chip topologies

Abstract Network on chip architecture provides a way to design complex integrated circuits with an objective to reduce connection issues, design productivity, and energy utilization. Network performance of a network is calculated by various factors but throughput is the most dominant characteristic for measuring network performance. So, this work includes investigation of various NoC topologies and analysis is done on basis of average throughput and average latency for ensuring network performance.

[1]  Thais Webber,et al.  Topological impact on latency and throughput: 2D versus 3D NoC comparison , 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

[2]  Abdul Quaiyum Ansari,et al.  Performance evaluation of various parameters of Network-on-Chip (NoC) for different topologies , 2015, 2015 Annual IEEE India Conference (INDICON).

[3]  Bevan M. Baas,et al.  Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Li Yubai,et al.  Design and simulation of a Torus topology for network on chip , 2008 .

[5]  Vikram Singh,et al.  PERFORMANCE EVALUATION OF RADIO PROPAGATION MODEL FOR VEHICULAR AD HOC NETWORKS USING VANET MOBI SIM AND NS-2 , 2012 .

[6]  Shivam Tyagi,et al.  Review of 3-D network-on-chip topologies , 2011, 2011 World Congress on Information and Communication Technologies.

[7]  Rached Tourki,et al.  A modular and generic router TLM model for speedup network-on-chip topology generation , 2013, 10th International Multi-Conferences on Systems, Signals & Devices 2013 (SSD13).

[8]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Seok-Bum Ko,et al.  A novel hybrid topology for Network on Chip , 2014, 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE).

[10]  Liang Yang,et al.  NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology , 2011 .

[11]  Yamin Li,et al.  A Cost and Performance Analytical Model for Large-Scale On-Chip Interconnection Networks , 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

[12]  Jong-Myon Kim,et al.  A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures , 2014, The Journal of Supercomputing.

[13]  Shlomo Weiss,et al.  Deflection Routing in Hierarchical Mesh NoCs , 2016, IEEE Embedded Systems Letters.

[14]  Ayas Kanta Swain,et al.  Performance assessment of different Network-on-Chip topologies , 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

[15]  Hiroki Matsutani,et al.  Balanced Dimension-Order Routing for k-ary n-cubes , 2009, 2009 International Conference on Parallel Processing Workshops.

[16]  Reena Dadhich,et al.  PERFORMANCE ANALYSIS OF ON-DEMAND ROUTING PROTOCOLS FOR VEHICULAR AD-HOC NETWORKS , 2011 .

[17]  Liang Yang,et al.  Performance analysis and comparison of 2 × 4 network on chip topology , 2012, Microprocess. Microsystems.

[18]  Ahmad Khademzadeh,et al.  MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems , 2009 .

[19]  Mohamed N. El-Derini,et al.  Using co-operating agents for partial results protection in mobile agent paradigm , 2009 .

[20]  Ramesh C. Poonia,et al.  Mobility Simulation of Reactive Routing Protocols for Vehicular Ad-hoc Networks , 2012 .

[21]  Jungang Han,et al.  A Mesh-Connected Rings Topology for Network-on-Chip , 2012, 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies.

[22]  Mohammad Ayoub Khan,et al.  Topologies and routing strategies in MPSoC , 2013, Int. J. Embed. Syst..

[23]  Abhijit Biswas,et al.  A topology for network-on-chip , 2016, 2016 International Conference on Information Communication and Embedded Systems (ICICES).

[24]  Lirong Qiu,et al.  An Efficient Scheme for Joint Compression and Encryption , 2014 .