Analysis of Power Efficient 6-T SRAM Cell with Performance Measurements

Among all the semiconductor memory modules available today, SRAM is considered to be the most critical and highly demanding semiconductor memory in the gamut of microelectronics applications as it does not require the need of regular refreshing. As the technology is continuously scaling down, it results in reduction of feature size along with the miniaturization at chip level. But along with this, the need of low power devices has also increased. But the genuine dilemma, especially for SRAM, is the leakage power. To solve leakage power problems, a large number of power reduction techniques are used. There are various advantages of using low power devices for example, the use of low power makes the device more portable with easy handling, improved battery life along with great improvement in the performance parameters. In processing as well as in memories and in data handling applications, devices with low power dissipation are in great demand. In this paper, the comparative study of various leakage power reduction techniques like Schmitt trigger, forced stack technique and LECTOR technique with SRAM architecture has been done. Simulation and analysis results show that the SRAM cell using forced stack technique attains lowest static power dissipation and total power dissipation along with all the advantages of the existing SRAM Cell. The simulation is done on the Symica DE and LT spice with 45 nm PTM technology.