Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century
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S. Grout | G. Ledenbach | R. G. Bushroe | P. Fisher | S. DasGupta | R. Steele | N. S. Nagaraj | A. Dengi
[1] M. Bohr. Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.
[2] Rajesh Gupta,et al. Design planning for high-performance ASICs , 1996, IBM J. Res. Dev..