Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century

This paper presents the description of the architecture of the Chip Hierarchical Design System (CHDS) and details on the required Timing Driven Physical Design capabilities that have been defined to satisfy the physical design needs for 0.25u technologies and beyond. These requirements are intended to solve the challenges including the Design Productivity Crisis identified by semiconductor industry, the shift in the design paradigm where the timing of a physical design will be dominated by interconnect effects, and the need for an integrated physical design system which still supports “plug-and-play” through the use of EDA standard languages, models, and interfaces.