The P2P Communication Model for a Local Memory based Multi-core Processor

Multi-core processor has become the mainstream processor nowadays. Data communication between different cores becomes a main problem especially when many cores need to get data from one core. Traditional Client/Server mode communication pattern tends to cause the server node to be the bottleneck and only uses the transfer path between the client and server nodes. A P2P communication model is proposed to solve this problem for a local memory based multi-core processor. It helps to alleviate the server core pressure and to form a multi-path transfer which makes full use of the bottom transfer network. Simulation results show that the proposed model provides a better performance than the traditional C/S mode communication which indicates that it is a promising communication model and can be used for other multi-core processors.

[1]  Seung-Ho Lee,et al.  MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[2]  David Ruimy Gonzales Micro-RISC architecture for the wireless market , 1999, IEEE Micro.

[3]  Damien Stolarz Peer-to-peer streaming media delivery , 2001, Proceedings First International Conference on Peer-to-Peer Computing.

[4]  Peter Marwedel,et al.  Scratchpad memory: a design alternative for cache on-chip memory in embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[5]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[6]  Henk Corporaal,et al.  MOVE: a framework for high-performance processor design , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[7]  Peter Pirsch,et al.  A multi-core SoC design for advanced image and video compression , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[8]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[9]  Ge Hai-tong Design of Communication Mechanisms for Dual-Core on Chip and Its Application , 2007 .

[10]  H. Peter Hofstee,et al.  Introduction to the Cell multiprocessor , 2005, IBM J. Res. Dev..