On circuit clustering for area/delay tradeoff under capacity and pin constraints
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[1] Robert K. Brayton,et al. On clustering for minimum delay/ara , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[2] Rajeev Murgai,et al. Speeding up technology-independent timing optimization by network partitioning , 1997, ICCAD 1997.
[3] Eugene L. Lawler,et al. Module Clustering to Minimize Delay in Digital Networks , 1969, IEEE Transactions on Computers.
[4] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .
[5] Rajeev Murgai,et al. Speeding up technology-independent timing optimization by network partitioning , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[6] Jason Cong,et al. Acyclic Multi-Way Partitioning of Boolean Networks , 1994, 31st Design Automation Conference.
[7] Rajmohan Rajaraman,et al. Optimal Clustering for Delay Minimization , 1993, 30th ACM/IEEE Design Automation Conference.
[8] Frank M. Johannes. Partitioning of VLSI circuits and systems , 1996, DAC '96.
[9] Martin D. F. Wong,et al. Circuit clustering for delay minimization under area and pin constraints , 1995, EDTC '95.