Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system

With the rapid increasing demand for high-performance computing, such as cloud computing, Tera (flops) scale high-performance computing system composed of hundreds of on-chip processing cores has become the recent interest. Given a large-scale computing system such as network-on-chip (NoC) with hundreds of cores, bandwidth and power density are the fundamental limits dominated by on-chip communication. This has brought extreme challenge when mapping application tasks onto Tera-scale NoC system. Previous task mapping scheme is mainly centralized and static, and hence results in large communication volume, not scalable for runtime task mapping required by Tera-scale NoC system. In order to improve on-chip traffic and reduce power density for the need of Tera-scale NoC system, we have proposed a de-centralized re-clustering algorithm. The processing cores in the NoC system are organized into clusters with an efficient decentralized re-clustering scheme to adjust the cluster size for the task mapping. As such, the communication volume can be significantly reduced and result in decreased power. Experimental results have demonstrated that our proposed algorithm can achieve reduction of communication traffic (up to 66.7%). The energy consumption profile has also been efficiently improved to reduce the hotspots.

[1]  Sharad Malik,et al.  A technology-aware and energy-oriented topology exploration for on-chip networks , 2005, Design, Automation and Test in Europe.

[2]  E. Carvalho,et al.  Congestion-aware task mapping in heterogeneous MPSoCs , 2008, 2008 International Symposium on System-on-Chip.

[3]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[4]  Suleyman Tosun New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs , 2011, J. Syst. Archit..

[5]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[6]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[7]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[8]  Saurabh Dighe,et al.  An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Samreen Amir,et al.  The Pivotal Role of Tera-scale Performance in Future Networks: Sequoia vs Multi-core Teraflop Chip , 2010, 2010 Second International Conference on Future Networks.

[11]  Fernando Gehm Moraes,et al.  Comparison of network-on-chip mapping algorithms targeting low energy consumption , 2008, IET Comput. Digit. Tech..

[12]  Shashi Kumar,et al.  A two-step genetic algorithm for mapping task graphs to a network on chip architecture , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[13]  Gerhard J. Woeginger,et al.  The Computational Complexity of the Minimum Weight Processor Assignment Problem , 2004, WG.

[14]  Daniël Paulusma,et al.  Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[15]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[16]  Jörg Henkel,et al.  ADAM: Run-time agent-based distributed application mapping for on-chip communication , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[17]  Fernando Gehm Moraes,et al.  Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[18]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[19]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .