Ultra-large scale integration

Ultra-large scale integration is governed by a hierarchical matrix of limits. The levels of this hierarchy can be codified as 1) fundamental, 2) material, 3) device, 4) circuit, and 5) system. Each level includes both theoretical and practical as well as analogical limits. Theoretically, thermal fluctuations impose a fundamental limit of several kT on switching energy. Scattering limited velocity and critical electric field establish a material limit on switching speed. Avoidance of punchthrough sets a device dimension limit. CMOS power-delay product defines a circuit limit. And, clock skew represents a system limit on ULSI. For conservative design margins, circuit limits project MOSFET channel lengths in the 0.4-0.2 µm range.

[1]  Gordon E. Moore,et al.  Progress in digital integrated electronics , 1975 .

[2]  H.I. Hanafi,et al.  An accurate and simple MOSFET model for computer-aided design , 1982, IEEE Journal of Solid-State Circuits.

[3]  J.D. Meindl.  Theoretical, practical and analogical limits in ULSI , 1983, 1983 International Electron Devices Meeting.

[4]  J. Bruning.  Optical imaging for microfabrication , 1980 .

[5]  K. Ratnakumar,et al.  Invited: Circuit scaling limits for ultra-large-scale integration , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  David M. Buss.  Technology and Design Challenges of MOS VLSI , 1981, ESSCIRC '81: 7th European Solid State Circuits Conference.

[7]  J. Meindl,et al.  Performance limits of NMOS and CMOS , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  K. N. Ratnakumar,et al.  Short-channel MOST threshold voltage model , 1982 .

[9]  K.C. Saraswat,et al.  Effect of scaling of interconnections on the time delay of VLSI circuits , 1982, IEEE Transactions on Electron Devices.

[10]  R.W. Keyes,et al.  Physical limits in digital electronics , 1975, Proceedings of the IEEE.

[11]  George E. Smith.  Sub-Micron NMOS Technology for High Speed VLSI , 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.

[12]  L. D. Yau,et al.  A simple theory to predict the threshold voltage of short-channel IGFET's , 1974 .

[13]  J. L. Moll,et al.  Design theory of a surface field-effect transistor , 1961 .

[14]  A. Broers,et al.  Resolution, overlay, and field size for lithography systems , 1981, IEEE Transactions on Electron Devices.

[15]  P.E. Cottrell,et al.  Multi-dimensional simulation of VLSI wiring capacitance , 1982, 1982 International Electron Devices Meeting.

[16]  R. Pease,et al.  High-performance heat sinking for VLSI , 1981, IEEE Electron Device Letters.

[17]  T.I. Kamins.  MOS Transistors in beam-recrystallized polysilicon , 1982, 1982 International Electron Devices Meeting.

[18]  Robert W. Keyes,et al.  The evolution of digital electronics towards VLSI , 1979 .

[19]  O. G. Folberth,et al.  The fundamental limitations of digital semiconductor technology , 1978 .

[20]  Joseph P. Martino,et al.  An introduction to technological forecasting , 1972 .

[21]  J. Meindl,et al.  Optimal interconnect circuits for VLSI , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[22]  J. Seto.  The electrical properties of polycrystalline silicon films , 1975 .

[23]  R. M. Swanson,et al.  Ion-implanted complementary MOS transistors in low-voltage circuits , 1972 .