A comprehensive approach to DRAM power management

This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe a simple power-down policy for exploiting low power modes of modern DRAMs; (2) we show how the idea of adaptive history-based memory schedulers can be naturally extended to manage power and energy; and (3) for situations in which additional DRAM power reduction is needed, we present a throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands. Using detailed microarchitectural simulators of the IBM Power5+ and a DDR2-533 SDRAM, we show that our first two techniques combine to increase DRAM energy efficiency by an average of 18.2%, 21.7%, 46.1%, and 37.1% for the Stream, NAS, SPEC2006fp, and commercial benchmarks, respectively. We also show that our throttling approach provides performance that is within 4.4% of an idealized oracular approach.

[1]  Ricardo Bianchini,et al.  Power and energy management for server systems , 2004, Computer.

[2]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[3]  Balaram Sinharoy,et al.  POWER4 system microarchitecture , 2002, IBM J. Res. Dev..

[4]  Calvin Lin,et al.  Adaptive History-Based Memory Schedulers for Modern Processors , 2006, IEEE Micro.

[5]  Luca Benini,et al.  Operating-system directed power reduction , 2000, ISLPED '00.

[6]  Luca Benini,et al.  Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques , 2003, TECS.

[7]  Sally A. McKee,et al.  Hardware Support for Dynamic Access Ordering: Performance of Some Design Options , 1993 .

[8]  Sally A. McKee,et al.  Design of a parallel vector access unit for SDRAM memory systems , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[9]  Mateo Valero,et al.  Command vector memory systems: high performance at low cost , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).

[10]  Carla Schlatter Ellis,et al.  Memory controller policies for DRAM power management , 2001, ISLPED '01.

[11]  Karthick Rajamani,et al.  A performance-conserving approach for reducing peak power consumption in server systems , 2005, ICS '05.

[12]  David H. Bailey,et al.  The Nas Parallel Benchmarks , 1991, Int. J. High Perform. Comput. Appl..

[13]  Calvin Lin,et al.  Adaptive History-Based Memory Schedulers , 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

[14]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[15]  Karthick Rajamani,et al.  Energy Management for Commercial Servers , 2003, Computer.

[16]  Mahmut T. Kandemir,et al.  Scheduler-based DRAM energy management , 2002, DAC '02.

[17]  Sandy Irani,et al.  Online strategies for dynamic power management in systems with multiple power-saving states , 2003, TECS.

[18]  Ricardo Bianchini,et al.  Limiting the power consumption of main memory , 2007, ISCA '07.

[19]  Alvin R. Lebeck,et al.  Power aware page allocation , 2000, SIGP.

[20]  Xiaodong Li,et al.  Performance directed energy management for main memory and disks , 2004, ASPLOS XI.

[21]  Calvin Lin,et al.  Enhancing memory controllers to improve dram power and performance , 2006 .

[22]  Calvin Lin,et al.  Memory scheduling for modern microprocessors , 2007, TOCS.

[23]  Mahmut T. Kandemir,et al.  DRAM energy management using software and hardware directed power mode control , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[24]  Balaram Sinharoy,et al.  IBM Power5 chip: a dual-core multithreaded processor , 2004, IEEE Micro.

[25]  Taewhan Kim,et al.  Memory access scheduling and binding considering energy minimization in multi-bank memory systems , 2004, Proceedings. 41st Design Automation Conference, 2004..

[26]  T. O. Kvålseth.  Cautionary Note about R 2 , 1985 .

[27]  Ivo Bolsens,et al.  Proceedings of the conference on Design, Automation & Test in Europe , 2000 .

[28]  Sanjeev Kumar,et al.  Dynamic tracking of page miss ratio curve for memory management , 2004, ASPLOS XI.

[29]  Mahmut T. Kandemir,et al.  Energy-oriented compiler optimizations for partitioned memory architectures , 2000, CASES '00.

[30]  Xiaobo Sharon Hu,et al.  Power aware variable partitioning and instruction scheduling for multiple memory banks , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[31]  Mahmut T. Kandemir.  Impact of data transformations on memory bank locality , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[32]  Kang G. Shin,et al.  Improving energy efficiency by making DRAM less randomly accessed , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[33]  Heekuck Oh,et al.  Neural Networks for Pattern Recognition , 1993, Adv. Comput..