Learning with memristive devices: How should we model their behavior?

This work discusses the modeling of memristive devices, for architectures where they are used as synapses. It is shown that the most common models used in this context do not always accurately reflect the actual behavior of popular devices in pulse regime. We introduce a new behavioral model, intended towards the nanoarchitecture community. It fits the conductance evolution of Univ. Michigan's synaptic memristive devices. A variation of the model fits HP labs's memristors' behavior in the same conditions. Finally, we discuss using a simple example the importance of this type of modeling for learning architectures and how it can impact the behavior of the learning.

[1]  H. Markram,et al.  Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs , 1997, Science.

[2]  C. Gamrat,et al.  An Organic Nanoparticle Transistor Behaving as a Biological Spiking Synapse , 2009, 0907.2540.

[3]  Bernabé Linares-Barranco,et al.  On neuromorphic spiking architectures for asynchronous STDP memristive systems , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[4]  Zhiyong Li,et al.  Ionic/Electronic Hybrid Materials Integrated in a Synaptic Transistor with Signal Processing and Learning Functions , 2010, Advanced materials.

[5]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[6]  D. Johnston,et al.  Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs , 1997 .

[7]  André DeHon,et al.  Array-based architecture for FET-based, nanoscale electronics , 2003 .

[8]  J. Yang,et al.  Switching dynamics in titanium dioxide memristive devices , 2009 .

[9]  R. Williams,et al.  Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior. , 2009, Small.

[10]  W. Lu,et al.  Programmable Resistance Switching in Nanoscale Two-terminal Devices , 2008 .

[11]  D. Strukov,et al.  CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .

[12]  Warren Robinett,et al.  Memristor-CMOS hybrid integrated circuits for reconfigurable logic. , 2009, Nano letters.

[13]  Wei Yang Lu,et al.  Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.

[14]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[15]  L. Chua Memristor-The missing circuit element , 1971 .

[16]  Dmitri B Strukov,et al.  Four-dimensional address topology for circuits with stacked multilayer crossbar arrays , 2009, Proceedings of the National Academy of Sciences.

[17]  Konstantin K. Likharev,et al.  Defect-tolerant nanoelectronic pattern classifiers: Research Articles , 2007 .

[18]  Shimeng Yu,et al.  Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory , 2011 .

[19]  Jacques-Olivier Klein,et al.  Hight fault tolerance in neural crossbar , 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[20]  G. Snider,et al.  Self-organized computation with unreliable, memristive nanodevices , 2007 .

[21]  Ieee Staff 2011 IEEE/ACM International Symposium on Nanoscale Architectures , 2011 .

[22]  J. Yang,et al.  Electrical transport and thermometry of electroformed titanium dioxide memristive switches , 2009 .

[23]  Wolfgang Maass,et al.  STDP enables spiking neurons to detect hidden causes of their inputs , 2009, NIPS.

[24]  Damien Querlioz,et al.  Simulation of a memristor-based spiking neural network immune to device variations , 2011, The 2011 International Joint Conference on Neural Networks.

[25]  R. Williams,et al.  Exponential ionic drift: fast switching and low volatility of thin-film memristors , 2009 .

[26]  W. Lu,et al.  CMOS compatible nanoscale nonvolatile resistance switching memory. , 2008, Nano letters.

[27]  Rainer Waser,et al.  Complementary resistive switches for passive nanocrossbar memories. , 2010, Nature materials.

[28]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[29]  Gregory S. Snider,et al.  Spike-timing-dependent learning in memristive nanodevices , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[30]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[31]  J. Simmons Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film , 1963 .

[32]  Jacques-Olivier Klein,et al.  Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  H. Hwang,et al.  An electrically modifiable synapse array of resistive switching memory , 2009, Nanotechnology.

[34]  Konstantin K. Likharev,et al.  Defect‐tolerant nanoelectronic pattern classifiers , 2007, Int. J. Circuit Theory Appl..

[35]  T. Berzina,et al.  Hybrid electronic device based on polyaniline-polyethyleneoxide junction , 2005 .

[36]  Massimiliano Di Ventra,et al.  Memristive model of amoeba learning. , 2008, Physical review. E, Statistical, nonlinear, and soft matter physics.

[37]  Massimiliano Versace,et al.  The brain of a new machine , 2010, IEEE Spectrum.

[38]  André DeHon,et al.  Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[39]  Wei Wu,et al.  A hybrid nanomemristor/transistor logic circuit capable of self-programming , 2009, Proceedings of the National Academy of Sciences.

[40]  Timothée Masquelier,et al.  Unsupervised Learning of Visual Features through Spike Timing Dependent Plasticity , 2007, PLoS Comput. Biol..

[41]  C. Gamrat,et al.  Nanotube devices based crossbar architecture: toward neuromorphic computing , 2010, Nanotechnology.