Performance Oriented Block-Based Neural Network Model by Parallelized Neighbor's Communication

The structure and weight in Block-Based Neural Network (BBNN) are optimized by utilizing the genetic algorithm. The architecture of BBNN consists of a two-dimensional (2-D) array of basic block with four input/output nodes and connection weights for block's output. To propose easier hardware implementation like Field Programmable Gate Array (FPGA), integer weights are used in the basic block. Each block can be one of the four different basic types and the architecture of BBNN is configured with the combination of basic blocks internally configured. However, BBNN's structural change needs hardware reconfiguration and the cost is very high. To reduce the reconfiguration cost, Smart Block-based Neuron (SBbN) which has sufficient number of weights for all four types of basic block has been proposed. SBbN preserves all weights, even the unnecessary for some types, and thus it consumes redundant hardware resource. A new model of BBNNs, in which all weights in SBbN are used efficiently by modifying calculation procedures of outputs in basic blocks, has been proposed and it eliminates the resource redundancy of SBbN. However, the new approach, which both right and left's side nodes concurrently serve as input and output, cannot provide parallel computation in right and left signal flow. This paper presents a pipelined parallel computation with independent side nodes for each signal flow.

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