GRAPH-BASED TRANSISTOR NETWORK GENERATION METHOD FOR SUPERGATE DESIGN

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products (SOP) expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches. The proposed method starts from a sum-ofproducts (SOP) form F and produces a reduced transistor network. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Keyword:sum-of-products (SOP) -parallel (SP), VLSI, Transistor-level, CMOS logic gates.