Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity
暂无分享,去创建一个
Lu Peng | Ying Zhang | Sui Chen | Shaoming Chen | Ying Zhang | Lu Peng | Shaoming Chen | Sui Chen
[1] Tajana Simunic,et al. Temperature aware thread block scheduling in GPGPUs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[2] Andrew B. Kahng. The ITRS design technology and system drivers roadmap: Process and status , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[3] Ishiuchi,et al. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .
[4] Sorin Cotofana,et al. Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices , 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).
[5] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .
[6] Kevin Skadron,et al. Rodinia: A benchmark suite for heterogeneous computing , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).
[7] Jaume Abella,et al. NBTI-Resilient Memory Cells with NAND Gates for Highly-Ported Structures , 2007 .
[8] Pradip Bose,et al. A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime , 2008, 2008 International Symposium on Computer Architecture.
[9] Scott A. Mahlke,et al. Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[10] Henry Wong,et al. Analyzing CUDA workloads using a detailed GPU simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.
[11] Luca Benini,et al. Aging-aware compiler-directed VLIW assignment for GPGPU architectures , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[12] Mahmut T. Kandemir,et al. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores , 2012, CODES+ISSS '12.
[13] Narayanan Vijaykrishnan,et al. Impact of NBTI on FPGAs , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[14] Ulf Schlichtmann,et al. Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[15] Yu Cao,et al. Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.
[16] M.A. Alam,et al. Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs , 2004, IEEE Transactions on Electron Devices.
[17] R. Degraeve,et al. Reliability Comparison of Triple-Gate Versus Planar SOI FETs , 2006, IEEE Transactions on Electron Devices.
[18] Josep Torrellas,et al. Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[19] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[20] Erika Gunadi,et al. Combating Aging with the Colt Duty Cycle Equalizer , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[21] Nam Sung Kim,et al. GPUWattch: enabling energy optimizations in GPGPUs , 2013, ISCA.
[22] Yu Cao,et al. Exploring sub-20nm FinFET design with Predictive Technology Models , 2012, DAC Design Automation Conference 2012.
[23] ミン・ヤン,et al. Hybrid planar and FinFETCMOS device , 2004 .
[24] Jaume Abella,et al. Penelope: The NBTI-Aware Processor , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[25] Zeshan Chishti,et al. Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures , 2003, MICRO.
[26] B. Kaczer,et al. Reliability issues in MuGFET nanodevices , 2008, 2008 IEEE International Reliability Physics Symposium.
[27] Hyesoon Kim,et al. Performance Analysis and Tuning for General Purpose Graphics Processing Units , 2012 .
[28] Donggun Park,et al. A study of negative-bias temperature instability of SOI and body-tied FinFETs , 2005, IEEE Electron Device Letters.
[29] A. Asenov,et al. Predicting future technology performance , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[30] Niraj K. Jha,et al. 3D vs. 2D analysis of FinFET logic gates under process variations , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).
[31] Richard W. Vuduc,et al. Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU) , 2012, Synthesis Lectures on Computer Architecture.
[32] Soha Hassoun,et al. Gate sizing: finFETs vs 32nm bulk MOSFETs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[33] Yuan Xie,et al. Dependability analysis of nano-scale FinFET circuits , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).