ALOE-Based Flexible LDPC Decoder
暂无分享,去创建一个
Guido Masera | Vuk Marojevic | Antoni Gelonch | Fabrizio Vacca | Ismael Gómez Miguelez | Jordi Bracke | Massimo Camatel | V. Marojevic | G. Masera | F. Vacca | A. Gelonch | Massimo Camatel | J. Bracke
[1] Narayanan Vijaykrishnan,et al. Implementing LDPC decoding on network-on-chip , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[2] Guido Masera,et al. Finite precision implementation of LDPC decoders , 2005 .
[3] Amer Baghdadi,et al. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.
[4] Vuk Marojevic,et al. A Lightweight Operating Environment for Next Generation Cognitive Radios , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.
[5] Sergio Benedetto,et al. Mapping interleaving laws to parallel turbo and LDPC decoder architectures , 2004, IEEE Transactions on Information Theory.
[6] Andreas Polydoros. Algorithmic aspects of radio flexibility , 2008, 2008 IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications.
[7] N. Wehn,et al. FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding , 2008, 2008 5th International Symposium on Turbo Codes and Related Topics.
[8] Gerhard Fettweis,et al. ASIP decoder architecture for convolutional and LDPC codes , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[9] Jun Tang,et al. Reconfigurable Shuffle Network Design in LDPC Decoders , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).
[10] D.E. Hocevar,et al. A reduced complexity decoder architecture via layered decoding of LDPC codes , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..
[11] Naresh R. Shanbhag,et al. Low-power VLSI decoder architectures for LDPC codes , 2002, ISLPED '02.
[12] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[13] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[14] Frank Kienle,et al. Disclosing the LDPC code decoder design space , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[15] Vuk Marojevic,et al. A Computing Resource Management Framework for Software-Defined Radios , 2008, IEEE Transactions on Computers.