Fast System-Level Area-Delay Curve Prediction

In this paper a unified approach of lower bound functional area and cycle budget estimations is presented to predict area–delay characteristics of designs at system level. The estimations are mainly based on relaxing precedence constraints in a behavioral design description and are the most accurate estimations reported to date.

[1]  Richard M. Karp,et al.  A n^5/2 Algorithm for Maximum Matchings in Bipartite Graphs , 1971, SWAT.

[2]  Hans Fleurkens.  Interactive system design in ESCAPE , 1993, [1993] Proceedings The Fourth International Workshop on Rapid System Prototyping.

[3]  Alok Sharma,et al.  Estimating Architectural Resources and Performance for High-Level Synthesis Applications , 1993, 30th ACM/IEEE Design Automation Conference.

[4]  J.T.J. van Eijndhoven,et al.  A data flow graph exchange standard , 1992, [1992] Proceedings The European Conference on Design Automation.

[5]  Alberto Sangiovanni-Vincentelli,et al.  A note on bipartite graphs and pivot selection in sparse matrices , 1976 .

[6]  A. H. Timmer,et al.  Execution interval analysis under resource constraints , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[7]  Jan Karel Lenstra,et al.  Complexity Results for Scheduling Tasks in Fixed Intervals on Two Types of Machines , 1982, SIAM J. Comput..

[8]  Minjoong Rim,et al.  Estimating lower-bound performance of schedules using a relaxation technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[9]  G. De Micheli,et al.  A module selection algorithm for high-level synthesis , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[10]  Peter B. Denyer,et al.  A new approach to pipeline optimisation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[11]  Alice C. Parker,et al.  Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Liang-Gee Chen,et al.  Optimal module set and clock cycle selection for DSP synthesis , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[13]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[14]  Richard M. Karp,et al.  A n^5/2 Algorithm for Maximum Matchings in Bipartite Graphs , 1971, SWAT.

[15]  A. H. Timmer,et al.  Module selection and scheduling using unrestricted libraries , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[16]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.