Testability measures with concurrent good simulation

Methods designed to speed up the computation of controllability within an event-driven fault-free simulation environment are described. Input generation techniques are presented which reduce the activity of the simulator, thus achieving a considerable speed-up. Concurrent simulation of fault-free devices is shown to be very effective in this domain. Experimental results are reported for benchmark circuits. No general law has been derived, but a rich set of heuristics has been collected which may be useful in many other cases.<<ETX>>

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