论文信息 - Analysis of a Digital Bit Synchronizer

Analysis of a Digital Bit Synchronizer

A simple digital bit synchronizer utilizing discrete phase control is discussed. The proposed system is intended for operation with NRZ coded binary signals. A finite state Markov chain model is used to evaluate the steady-state phase jitter performance of the bit synchronizer in the presence of additive white Gaussian noise. The theoretical results are confirmed by computer simulation. The same mathematical model is used to investigate the transient (acquisition) performance of the synchronizer. Finally, the performance of the synchronizer as a data detector is discussed and the error probability performance is compared with that of the optimum detector.

A. Payzin

[1] D. Levy,et al. Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise , 1972, IEEE Trans. Commun..

[2] J. Ransom,et al. Performance of a Finite Phase State Bit-Synchronization Loop with and Without Sequential Filters , 1975, IEEE Trans. Commun..

[3] W. J. Hurd,et al. Digital Transition Tracking Symbol Synchronizer for LOW SNR Coded Systems , 1970 .

[4] Richard D. Gitlin,et al. Timing recovery in PAM systems , 1971 .

[5] J. J. Stiffler,et al. Theory of synchronous communications , 1971 .

[6] Marvin K. Simon. Nonlinear Analysis of an Absolute Value Type of an Early-Late Gate Bit Synchronizer , 1970 .

[7] S. Mori,et al. Performance of Binary Quantized All Digital Phase-Locked Loop with a New Class of Sequential Filter , 1978, IEEE Trans. Commun..

[8] K. Mueller,et al. Timing Recovery in Digital Synchronous Data Receivers , 1976, IEEE Trans. Commun..

[9] Marvin K. Simon. Optimization of the Performance of a Digital-Data-Transition Tracking Loop , 1970 .