Design and Hardware Implementation of a STT-MRAM Based SoC Architecture for Smart Card Chip

As the widely studied next-generation memory, spin-torque transfer random access memory (STT-MRAM) has a tendency to replace the traditional memory architecture. In this paper, the feasibility of integrating STT-MRAM into resources constrained IoT application is researched. Then a System-on-Chip (SoC) architecture based on STT-MRAM for smart card chip is proposed. Prototype verification results on a DE2 FPGA platform demonstrate that the STT-MRAM based SoC architecture can greatly improve the performance of both the ECC and AES coprocessor. According to the synthesis result in SMIC 40nm CMOS technology, the equivalent gate area of the STT-MRAM based SoC is 88K and the average power consumption is 3.284mW. All of those characteristics make the realization of STT-MRAM based SoC architecture for smart card chip promising.