Reliability analysis of logic circuits using binary probabilistic transfer matrix

Technology scales strongly increased the sensitivity of new integrated logic circuits to transient faults. Since the reliability of combinational circuit is an important factor in digital circuits design, so, a fast method to obtain accurate value of reliability becomes a main challenge. The main source of inaccuracy and scalability problems in existing methods is the presence of reconverging signals. In this paper a new library-based method is proposed to calculate the circuit reliability in which the effects of nested reconvergent paths is considered easily. So a binary probability matrix is used to resolve signals correlation problem. Simulation results show that our proposed method gives accurate reliability value with less complexity than previous methods.

[1]  Farshad Firouzi,et al.  An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects , 2011, Microelectron. Reliab..

[2]  Sandeep K. Shukla,et al.  Scalable techniques and tools for reliability analysis of large circuits , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[3]  Hao Chen,et al.  Stochastic computational models for accurate reliability evaluation of logic circuits , 2010, GLSVLSI '10.

[4]  P. Hazucha,et al.  Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process , 2000, IEEE Journal of Solid-State Circuits.

[5]  Mehdi Baradaran Tahoori,et al.  A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[6]  Afshin Abdollahi.  Probabilistic decision diagrams for exact probabilistic analysis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Denis Teixeira Franco,et al.  Signal probability for reliability evaluation of logic circuits , 2008, Microelectron. Reliab..

[8]  Hao Chen,et al.  A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

[9]  John P. Hayes,et al.  Probabilistic transfer matrices in symbolic reliability analysis of logic circuits , 2008, TODE.

[10]  Massoud Pedram,et al.  Probabilistic error propagation in logic circuits using the Boolean difference calculus , 2008, 2008 IEEE International Conference on Computer Design.

[11]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[12]  Roy C. Ogus,et al.  The Probability of a Correct Output from a Combinational Circuit , 1975, IEEE Transactions on Computers.

[13]  Lirida A. B. Naviner,et al.  Fast reliability analysis of combinatorial logic circuits using conditional probabilities , 2010, Microelectron. Reliab..

[14]  Sandeep K. Shukla,et al.  NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures , 2004, GLSVLSI '04.

[15]  Oana Boncalo,et al.  Two phase reliability analysis of quantum circuits in a block based approach , 2009 .

[16]  Kartik Mohanram,et al.  Accurate and scalable reliability analysis of logic circuits , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[17]  Denis Teixeira Franco,et al.  Reliability analysis of logic circuits based on signal probability , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[18]  Sanjukta Bhanja,et al.  Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[20]  Kartik Mohanram,et al.  Reliability Analysis of Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  David Blaauw,et al.  Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Mehdi Baradaran Tahoori,et al.  An accurate SER estimation method based on propagation probability [soft error rate] , 2005, Design, Automation and Test in Europe.

[23]  J. M. Kontoleon,et al.  Exact reliability analysis of combinational logic circuits , 1988 .

[24]  Kia Bazargan,et al.  Estimation and optimization of reliability of noisy digital circuits , 2009, 2009 10th International Symposium on Quality Electronic Design.

[25]  Yuan Xie,et al.  Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model , 2011, IEEE Transactions on Dependable and Secure Computing.

[26]  J. Hayes,et al.  Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models , 2003 .