A new poly-Si TG-TFT with diminished pseudosubthreshold region: theoretical investigation and analysis
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[1] H. Mizuta,et al. Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel , 2004, IEEE Transactions on Electron Devices.
[2] R. E. Thomas,et al. Carrier mobilities in silicon empirically related to doping and field , 1967 .
[3] J. Colinge. Silicon-on-Insulator Technology , 1991 .
[4] J. Seto. The electrical properties of polycrystalline silicon films , 1975 .
[5] M. J. Kumar,et al. Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.
[6] H. Shichijo,et al. Anomalous leakage current in LPCVD PolySilicon MOSFET's , 1985, IEEE Transactions on Electron Devices.
[7] Kikuo Ono,et al. An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits , 1993, Proceedings of IEEE International Electron Devices Meeting.
[8] M.J. Kumar,et al. A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation , 2005, IEEE Transactions on Nanotechnology.
[9] R. Carluccio,et al. Lateral growth control in excimer laser crystallized polysilicon , 1999 .
[10] M.J. Kumar,et al. Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.
[11] H. Ohno,et al. Modeling and simulation of polycrystalline ZnO thin-film transistors , 2003 .
[12] Masaki Hara,et al. High performance poly-Si TFTs fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing , 1995 .
[13] Giorgio Baccarani,et al. Transport properties of polycrystalline silicon films , 1978 .
[14] N. Sasaki,et al. High performance poly-Si TFTs on a glass by a stable scanning CW laser lateral crystallization , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[15] A proposed single grain-boundary thin-film transistor , 2001, IEEE Electron Device Letters.
[16] Satoshi Takenaka,et al. Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors , 1992 .
[17] Haitao Liu,et al. Characteristics of high-K spacer offset-gated polysilicon TFTs , 2004, IEEE Transactions on Electron Devices.
[18] T. Shimoda,et al. Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density , 2001 .
[19] P. J. Scanlon,et al. Conductivity behavior in polycrystalline semiconductor thin film transistors , 1982 .
[20] Pole-Shang Lin,et al. On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size , 1993, IEEE Electron Device Letters.
[21] J. R. Ayres,et al. High-speed, short-channel polycrystalline silicon thin-film transistors , 2004 .
[22] Yasuhiro Mochizuki,et al. Inverse staggered poly-Si and amorphous Si double structure TFT's for LCD panels with peripheral driver circuits integration , 1996 .
[23] N. Sano,et al. Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors , 2003 .
[24] J. Jeon,et al. A new polycrystalline silicon TFT with a single grain boundary in the channel , 2001 .
[25] P. Carey,et al. Low-temperature single-crystal Si TFTs fabricated on Si films processed via sequential lateral solidification , 1998, IEEE Electron Device Letters.
[26] M.J. Kumar,et al. Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET , 2004, IEEE Transactions on Electron Devices.
[27] Michael S. Shur,et al. Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs , 1996 .