Rapid estimation for parameterized components in high-level synthesis

An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the synthesized RT design, and thus need to be supported by fast and accurate estimators for these parameterized RT-components. Ideally, one would like to obtain the actual area and delay attributes of each component by constructing (or generating) the designs. However, such constructive methods require excessive run times, prohibiting on-line integration with the tasks of scheduling and allocation. This paper describes a fast (constant-time) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. The authors performed an extensive set of experiments to validate the estimation technique on combinational as well as sequential RT component generators. The results show a prediction of the area and delay to within 10% of the actual values. These models have also been integrated with a high-level synthesis system to permit on-line estimation of a component's area and delay. >

[1]  David E. Wallace,et al.  High-level delay estimation for technology-independent logic equations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[2]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Forrest Brewer.  Constraint driven behavioral synthesis , 1988 .

[4]  Fadi J. Kurdahi,et al.  LAST: a layout area and shape function estimator for high level applications , 1991, Proceedings of the European Conference on Design Automation..

[5]  Nikil Dutt.  Generic component library characterization for high level synthesis , 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

[6]  F.J. Kurdahi,et al.  TELE: a timing evaluator using layout estimation for high level applications , 1992, [1992] Proceedings The European Conference on Design Automation.

[7]  Wayne H. Wolf,et al.  How to build a hardware description and measurement system on an object-oriented programming language , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Akhilesh Tyagi.  An algebraic model for design space with applications to function module generation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[9]  Fadi J. Kurdahi,et al.  Techniques for area estimation of VLSI layouts , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Rajiv Jain,et al.  Area-time model for synthesis of non-pipelined designs , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[11]  Nikil D. Dutt,et al.  Bridging high-level slqvihesis to RTL technology libraries , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  M. Morris Mano,et al.  Computer Engineering: Hardware Design , 1988 .

[13]  Daniel D. Gajski,et al.  Synthesis from VHDL , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[14]  Rajiv Jain.  MOSP: module selection for pipelined designs with multi-cycle operations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  Nikil Dutt.  GENUS : a generic component library for high level synthesis , 1988 .

[16]  Viraphol Chaiyakul,et al.  Layout-area models for high-level synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[17]  Viraphol Chaiyakul,et al.  Timing models for high-level synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[18]  D.D. Gajski,et al.  An algorithm for component selection in performance optimized scheduling , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[19]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .