Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array

This paper introduces a self-optimizing processor/coprocessor model supported by a feedback control system to achieve power efficiency. The software on the processor receives high-level performance constraints (i.e., real-time limits) as goal from the user and in return controls the clock speed of the coprocessor and memories, ensuring the performance constraints are met while minimizing power dissipation. The system is prototyped on a Stratix-V Field Programmable Gate Array device. The self-optimization feature requires less than 0.5% of the overall logic resources and provides a 33% reduction in average dynamic power dissipation when the control system activates for a proof-of-concept test case derived from Fast Fourier Transform processing at the IEEE-802.11n demodulator.

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