VLSI architectures for forward error-control decoders
暂无分享,去创建一个
Naresh R. Shanbhag | Arshad Ahmed | Seok Jun Lee | Mohammad M. Mansour | Naresh R Shanbhag | Seok-Jun Lee | Arshad Ahmed
[1] Francky Catthoor,et al. Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design , 1998 .
[2] Naresh R. Shanbhag,et al. Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[3] V. Benes. Optimal rearrangeable multistage connecting networks , 1964 .
[4] W. Wilhelm. A new scalable VLSI architecture for Reed-Solomon decoders , 1999 .
[5] Teresa H. Meng,et al. A 140-Mb/s, 32-state, radix-4 Viterbi decoder , 1992 .
[6] Elwyn R. Berlekamp,et al. Algebraic coding theory , 1984, McGraw-Hill series in systems science.
[7] Rüdiger L. Urbanke,et al. Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.
[8] C. E. SHANNON,et al. A mathematical theory of communication , 1948, MOCO.
[9] Robert T. Chien,et al. Cyclic decoding procedures for Bose- Chaudhuri-Hocquenghem codes , 1964, IEEE Trans. Inf. Theory.
[10] Jah-Ming Hsu,et al. A parallel decoding scheme for turbo codes , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[11] Naresh R. Shanbhag,et al. Toward achieving energy efficiency in presence of deep submicron noise , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[12] Alexander Vardy,et al. Algebraic soft-decision decoding of Reed-Solomon codes , 2003, IEEE Trans. Inf. Theory.
[13] G. Bauch. A comparison of soft-in/soft-out algorithms for 'turbo-detection' , 1998 .
[14] Naresh R. Shanbhag,et al. VLSI architectures for SISO-APP decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[15] Sergio Benedetto,et al. A soft-input soft-output maximum a posteriori (MAP) module to decode parallel and serial concatenated codes , 1996 .
[16] Judea Pearl,et al. Probabilistic reasoning in intelligent systems - networks of plausible inference , 1991, Morgan Kaufmann series in representation and reasoning.
[17] J. Rotman. Advanced Modern Algebra , 2002 .
[18] A. Glavieux,et al. Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.
[19] John Cocke,et al. Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.
[20] M. Bickerstaff,et al. A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[21] G. David Forney,et al. Generalized minimum distance decoding , 1966, IEEE Trans. Inf. Theory.
[22] H. Suzuki,et al. A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder , 2000, IEEE Journal of Solid-State Circuits.
[23] Robert Michael Tanner,et al. A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.
[24] Naresh R. Shanbhag,et al. Architecture-aware low-density parity-check codes , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[25] Jaap C. Haartsen,et al. The Bluetooth radio system , 2000, IEEE Personal Communications.
[26] J. Bibb Cain,et al. Error-Correction Coding for Digital Communications , 1981 .
[27] Gordon E. Moore,et al. Progress in digital integrated electronics , 1975 .
[28] Payam Pakzad,et al. VLSI architectures for iterative decoders in magnetic recording channels , 2001 .
[29] Jung-Fu Cheng,et al. Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm , 1998, IEEE J. Sel. Areas Commun..
[30] Jiang Wu,et al. 4th-generation Wireless Infrastructures: Scenarios and Research Challenges , 2001, IEEE Wirel. Commun..
[31] B. Nikolic,et al. Implementation of high throughput soft output Viterbi decoders , 2002, IEEE Workshop on Signal Processing Systems.
[32] R. Kotter. Fast generalized minimum-distance decoding of algebraic-geometry and Reed-Solomon codes , 1996 .
[33] R. Blahut. Algebraic Codes for Data Transmission , 2002 .
[34] Claude Berrou,et al. A low complexity soft-output Viterbi decoder architecture , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.
[35] Naresh R. Shanbhag,et al. High-speed architectures for Reed-Solomon decoders , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[36] Behrooz Parhami,et al. Computer arithmetic - algorithms and hardware designs , 1999 .
[37] Thomas Noll,et al. Implementation of scalable power and area efficient high-throughput Viterbi decoders , 2002 .
[38] Naresh R. Shanbhag,et al. Design methodology for high-speed iterative decoder architectures , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[39] Sae-Young Chung,et al. On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit , 2001, IEEE Communications Letters.
[40] Naresh R. Shanbhag,et al. Low-power turbo equalizer architecture , 2002, IEEE Workshop on Signal Processing Systems.
[41] Joachim Hagenauer,et al. A Viterbi algorithm with soft-decision outputs and its applications , 1989, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond.
[42] Mohammad M. Mansour. High-performance decoders for regular and irregular repeat-accumulate codes , 2004, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04..
[43] Dariush Divsalar,et al. Coding theorems for 'turbo-like' codes , 1998 .
[44] Naresh R. Shanbhag,et al. Turbo decoder architectures for low-density parity-check codes , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.
[45] Brendan J. Frey,et al. Iterative Decoding of Compound Codes by Probability Propagation in Graphical Models , 1998, IEEE J. Sel. Areas Commun..
[46] Naresh R. Shanbhag,et al. High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[47] C. Rader. Memory Management in a Viterbi Decoder , 1981, IEEE Trans. Commun..
[48] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[49] Jr. G. Forney,et al. The viterbi algorithm , 1973 .
[50] Teresa H. Y. Meng,et al. Hybrid survivor path architectures for Viterbi decoders , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[51] G. David Forney,et al. On decoding BCH codes , 1965, IEEE Trans. Inf. Theory.
[52] Naresh R. Shanbhag,et al. A low-power VLSI architecture for turbo decoding , 2003, ISLPED '03.