Buffer planning for 3D ICs

With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer insertion, as another approach to reduce wire delay, is still necessary to further optimize interconnects. In this paper, a buffer planning algorithm at floorplanning stage for 3D ICs is proposed. Firstly, we reduce buffer insertion to a dynamic programming path problem. Then we show its potential to handle the 3D buffer insertion problem. At the same time, vertical interlayer vias are also planned. At last, buffer planning is integrated with floorplanning to optimize the packing so that not only area and wire length reach a satisfying value, timing performance is also optimized.

[1]  Yao-Wen Chang,et al.  TCG: a transitive closure graph-based representation for non-slicing floorplans , 2001, DAC '01.

[2]  Jason Cong,et al.  Buffer block planning for interconnect-driven floorplanning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[3]  Martin D. F. Wong,et al.  FAST-SP: a fast algorithm for block placement based on sequence pair , 2001, ASP-DAC '01.

[4]  Mansun Chan,et al.  Development of a viable 3D integrated circuit technology , 2001, Science in China Series : Information Sciences.

[5]  A. Fan,et al.  Copper Wafer Bonding , 1999 .

[6]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[8]  Sheqin Dong,et al.  3D CBL: An Efficient Algorithm for General 3-Dimensional Packing Problems * , 2005 .

[9]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[10]  Yangdong Deng,et al.  Interconnect characteristics of 2.5-D system integration scheme , 2001, ISPD '01.

[11]  Liang Deng,et al.  Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, Proceedings of International Conference on Computer Aided Design.

[13]  Jun Gu,et al.  Buffer planning as an Integral part of floorplanning with consideration of routing congestion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Sheqin Dong,et al.  Floorplanning for 2.5-D system integration using multi-layer-BSG structure , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[15]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[16]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990, IEEE International Symposium on Circuits and Systems.

[17]  Yici Cai,et al.  Corner block list representation and its application to floorplan optimization , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Yici Cai,et al.  Evaluating a bounded slice-line grid assignment in O(nlogn) time , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[19]  Cheng-Kok Koh,et al.  Routability-driven repeater block planning for interconnect-centric floorplanning , 2000, ISPD '00.