WARNING: 100% Fault Coverage May Be Misleading!!

In this gaper we show that even when a sequential test generator does a "perfect" job and achieves 100% detectable fault coverage, a circuit passing the test may still exhibit severe testability problems caused by undetectable faults that prevent initialization (FPIs). Thus 100% fault coverage may be a misleading quality indicator, unless undetectable FPIs are accounted for. We present the first algorithm able to identify undetectable FPIs and we report the results obtained for the sequential benchmark circuits. We also discuss the design for testability techniques that make these faults detectable.

[1]  Melvin A. Breuer.  A Note on Three-Valued Logic Simulation , 1972, IEEE Transactions on Computers.

[2]  Melvin A. Breuer,et al.  On Redundancy and Fault Detection in Sequential Circuits , 1979, IEEE Transactions on Computers.

[3]  Irith Pomeranz,et al.  Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Kwang-Ting Cheng.  On removing redundancy in sequential circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[6]  Takuji Ogihara,et al.  Test generation for sequential circuits using individual initial value propagation , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[7]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.

[8]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[9]  Irith Pomeranz,et al.  Test generation for synchronous sequential circuits using multiple observation times , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[10]  M. Abramovici,et al.  SMART And FAST: Test Generation for VLSI Scan-Design Circuits , 1986, IEEE Design & Test of Computers.

[11]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .