A high throughput ASIC design for IPv6 routing lookup system

This paper presents a cache-centric, hash-based architecture within a application specific integrated circuit (ASIC) implementation for IPv6 routing lookup system. In ASIC, the binary content addressable memory (BCAM) as cache memory has a hit ratio of up to 80% with a FIFO replacement algorithm. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The results of postlayout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100 Gbps networks. The routing table only needs 10.24KB on-chip BCAM, 20.04KB offchip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.

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