A method to perform error simulation in VHDL ∗

∗ This work has been partially funded by TOMI project (ESPRIT #20724) Abstract: This paper describes a method to perform error simulation to estimate the quality of the testbenches used to validate VHDL designs. The method is based in the mutation of VHDL descriptions by an error model. The proposed method allows an automatic execution of the error simulation using a commercial VHDL simulator. The resulting tool will be integrated in an environment devoted to quality checking of VHDL designs.