A Study on Low Power Buffer Design for Video Processing Systems

Power consumption is the most concern in the high performance portable systems. This paper presents some techniques for designing data buffer in video processing systems. The major component of power dissipation is due to the data switching and clocking activities on system buses and buffers. Therefore, we consider applying power-reduction schemes for data buses and buffers using a combination of frame buffer tiling, SRAM/SDRAM configuring, and data bus width optimizing. The correct design can significantly reduce the power consumption of the digital video systems.