Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits

This paper reviews the circuit design considerations of scaled sub-0.1 /spl mu/m partially-depleted SOI (PD/SOI) CMOS circuits for high-performance digital applications. The impact of technology/device scaling and design challenges are highlighted. Unique design aspects and issues resulting from the scaling of PD/SOI device structure, such as parasitic bipolar effect and reduced-V/sub T/ leakage, hysteretic V/sub T/ variation, low-voltage impact ionization, higher V/sub T,lin/ to maintain adequate V/sub T,sat/, scaling/thinning of Si film, gate-to-body tunneling current, self-heating, soft error rate (SER), and the introduction of strained-Si channel on SOI are addressed.

[1]  Ching-Te Chuang,et al.  Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[2]  M. Asheghi,et al.  Thermal conductivity model for thin silicon-on-insulator layers at high temperatures , 2002, 2002 IEEE International SOI Conference.

[3]  Ching-Te Chuang,et al.  Effects of Gate-to-Body Tunneling Current on PD/SOI CMOS Circuits , 2001 .

[4]  Ching-Te Chuang,et al.  Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology , 2001 .

[5]  M. Ieong,et al.  Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[6]  Ching-Te Chuang,et al.  Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits , 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

[7]  Kenneth L. Shepard,et al.  Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[8]  C. Tretz,et al.  Hysteresis in floating-body PD/SOI CMOS circuits , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[9]  K. Bernstein,et al.  Soft error rate scaling for emerging SOI technology options , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[10]  Theodore W. Houston,et al.  A guide to simulation of hysteretic gate delays based on physical understanding [SOI logic] , 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

[11]  Toshihiro Sugii,et al.  Self-heating enhanced impact ionization in SOI MOSFETs , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[12]  A. Wei,et al.  Design methodology for minimizing hysteretic V/sub T/-variation in partially-depleted SOI CMOS , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[13]  A. Wei,et al.  Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS , 1996, IEEE Electron Device Letters.

[14]  C. Chuang,et al.  Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits , 2002, 2002 IEEE International SOI Conference.

[15]  K. Rim.  Strained Si surface channel MOSFETs for high-performance CMOS technology , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[16]  Ching-Te Chuang,et al.  Floating-body effects in partially depleted SOI CMOS circuits , 1997 .

[17]  M. Sherony,et al.  Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[18]  Tahir Ghani,et al.  Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[19]  Rajiv V. Joshi,et al.  Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[20]  C. T. Chuang,et al.  A tri-state body charge modulated SOI sense amplifier , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[21]  I. Aller,et al.  Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[22]  Ali M. Niknejad,et al.  An Impact Ionization Model for SO1 Circuit Simulation , 2002 .

[23]  Ching-Te Chuang,et al.  SOI digital CMOS VLSI—a design perspective , 1999, DAC '99.

[24]  Chenming Hu,et al.  Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[25]  Ching-Te Chuang,et al.  Dual-mode Parasitic Bipolar Effect In Dynamic CVSL XOR Circuit With Floating-body Partially-depleted SOI Devices , 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

[26]  M. Chan,et al.  An impact ionization model for SOI circuit simulation [MOSFETs] , 2002, 2002 IEEE International SOI Conference.

[27]  Ching-Te Chuang,et al.  A dynamic body discharge technique for SOI circuit applications , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[28]  Ching-Te Chuang,et al.  Measurement of history effect in PD/SOI single-ended CPL circuit , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[29]  R. V. Joshi,et al.  3D Thermal Analysis for SOI and its impact on Circuit Performance , 2001 .

[30]  H.-S.P. Wong,et al.  Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[31]  Ching-Te Chuang,et al.  SOI for digital CMOS VLSI: design considerations and advances , 1998, Proc. IEEE.

[32]  Y. Tosaka,et al.  /spl alpha/-particle-induced soft errors in submicron SOI SRAM , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.