A scheme to reduce active leakage power by detecting state transitions

Active leakage power is predicted to become dominant in the total power consumption as the transistor gets scaled. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125/spl deg/C, is facing at difficulties such as throughput degradation of testing due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel technique to reduce active leakage power of finite-state-machines (FSM's) at run time. Combinational logic gates are dynamically disconnected from the ground to reduce leakage when state transitions do not occur. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 /spl mu/m technology. The total power was reduced by 20% at the maximum at 125/spl deg/C. It was also found that performance degradation was tolerable for burn-in testing.