Data Retention Characterization of Phase-Change Memory Arrays

To support reliable large array products, phase-change memory (PCM) technologies must be able to retain data over the product's lifetime with very low defect rates. PCM stores data in a chalcogenide material which can be placed in either a high resistance amorphous phase or a low resistance crystalline phase. Data retention is limited by resistance loss of the amorphous phase of the material, a process that is controlled by the kinetics of crystallization. This paper presents array-level data retention results on a statistical distribution of PCM cells that shows the failure rate with temperature to be well-described by the Arrhenius equation and distributed lognormally with time. For typical cells, the retention capability exceeds 100,000 hours at 85degC and is capable of meeting product requirements. In non-optimized devices, however, we observe cells that fail earlier than the lognormal distribution would predict. The failure distribution of these cells is Weibull with time but shows similar temperature acceleration to the intrinsic distribution, indicative of a defect in the amorphous chalcogenide. Characterization of these cells shows that their retention behavior is erratic. Furthermore, it is not significantly changed by write cycling. We then show that this defect distribution can be suppressed by process architecture or write algorithm optimization. Retention data collected on cells at both the 180nm and 90nm lithography nodes show that the intrinsic behavior is maintained with process scaling