A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators

This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process. It is observed that Lognormal distribution represents RTN induced delay distribution well. RTN model of gate size dependency is then developed and validated using the measured data. Model based delay distribution estimation and measurement match well. The proposed extraction methodology is thus suitable for estimating RTN of transistors with arbitrary gate size. The model helps reliability and worst case analysis of digital circuits where transistors of various gate sizes are used.

[1]  Nobuyuki Sugii,et al.  Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[2]  H. Onodera,et al.  Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization , 2013, IEEE Transactions on Semiconductor Manufacturing.

[3]  L. Fenton.  The Sum of Log-Normal Probability Distributions in Scatter Transmission Systems , 1960 .

[4]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[5]  D. Frank,et al.  Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm , 2006, 2009 Symposium on VLSI Technology.

[6]  P. McLane,et al.  Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications , 1994, International Conference on Communications.

[7]  Hidetoshi Onodera,et al.  In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators , 2014, 2014 International Conference on Microelectronic Test Structures (ICMTS).

[8]  T. Matsumoto,et al.  Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation , 2012, 2012 International Electron Devices Meeting.

[9]  M. D. Giles,et al.  Random telegraph noise (RTN) in 14nm logic technology: High volume data extraction and analysis , 2016, 2016 IEEE Symposium on VLSI Technology.

[10]  Ru Huang,et al.  New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits , 2014, 2014 IEEE International Electron Devices Meeting.

[11]  K. Takeuchi,et al.  Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude , 2006, 2009 Symposium on VLSI Technology.

[12]  A. Visconti,et al.  Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.