Soft-programmable bypass switch design for defect-tolerant arrays

Most wafer-scale processing arrays include bypass switches and wiring to permit signals to be routed around faulty modules. In some cases, the bypass circuitry contains registers to maintain data synchronization. The ideal switch design maximizes routing flexibility and switch yield while minimizing switch area and signal delay. Unfortunately these design goals work at cross-purposes. The goals also vary in importance, depending on the wafer architecture. For example, some architectures can cope with bypass logic failures, while others cannot. The ability to cope with failures may be a function of the failure mode. The author examines a number of bypass switch circuit and layout designs, and how well they meet to the design goals. He uses the DVLASIC distributed catastrophic fault yield simulator to perform yield computations.<<ETX>>