A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications

This paper describes a quantization noise reduction method in DeltaSigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.

[1]  Michiel Steyaert,et al.  A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μM CMOS , 1996, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[2]  Jan Craninckx,et al.  A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .

[3]  Bang-Sup Song,et al.  A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order ΔΣ modulator , 2000 .

[4]  Juha Kostamovaara,et al.  Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers , 2003 .

[5]  D. Jeong,et al.  A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  Bang-Sup Song,et al.  A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[7]  M.H. Perrott,et al.  A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise , 2006, IEEE Journal of Solid-State Circuits.

[8]  D.L. Kaczman,et al.  A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver , 2006, IEEE Journal of Solid-State Circuits.

[9]  H. Hedayati,et al.  Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers , 2006, IEEE Transactions on Microwave Theory and Techniques.

[10]  Ian Galton,et al.  A Wide-Bandwidth 2.4 GHz ISM Band Fractional-$N$ PLL With Adaptive Phase Noise Cancellation , 2007, IEEE Journal of Solid-State Circuits.

[11]  Zhihua Wang,et al.  A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.