论文信息 - Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

[1] T. Numata,et al. Short-channel performance and mobility analysis of <110>- and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions , 2010, 2010 Symposium on VLSI Technology.

[2] Toshiro Hiramoto,et al. Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range , 2010, 2010 Symposium on VLSI Technology.

[3] T. Hiramoto,et al. Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI , 2008, 2008 Symposium on VLSI Technology.