Design of new high-speed and low-energy dynamic PLA

Programmable logic arrays (PLAs) are popular devices in the realisation of circuits as it can implement any Boolean function. This article proposes a dynamic complementary metal oxide semiconductor (CMOS) PLA based on NOR architecture that uses a secondary clock and feedback phenomena for low energy and high speed. Static power reduction is achieved by blocking the static current flow during evaluation period. The proposed design is simulated at 45 nm CMOS technology using CADENCE VLSI design tool. With respect to the latest low-energy and fastest PLA reported in the literature, the proposed design is 69% faster and consumes 73% less energy.

[1]  G. M. Blair,et al.  PLA design for single-clock CMOS , 1992 .

[2]  Jinn-Shyan Wang,et al.  Analysis and design of high-speed and low-power CMOS PLAs , 2001 .

[3]  GU Donghuicharles,et al.  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE , 2008 .

[4]  Kai-Cheng Wei,et al.  Using the charge recycling technique for low power PLA design , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[5]  Lee-Sup Kim,et al.  A high performance low power dynamic PLA with conditional evaluation scheme , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[6]  Resve A. Saleh,et al.  Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[7]  Yongsheng Yin,et al.  A new approach to Programmable Logic Array for single-clock CMOS , 2006 .

[8]  Shahriar Mirabbasi,et al.  A high-speed low-energy dynamic PLA using an input-isolation scheme , 2006, 2006 IEEE International Symposium on Circuits and Systems.