A new low power multiplexer based ternary multiplier using CNTFETs

Abstract In the following paper, a single bit ternary multiplier utilizing carbon nanotube field-effect transistor (CNTFET) has been presented. Almost in the ternary circuit design, only one supply voltage VDD is used and a voltage division circuit is activated to produce VDD/2 for logic ‘1’, So the direct current from VDD to ground increases the static power considerably. In This paper, using two supply voltages, VDD and VDD/2, the circuit is designed so as VDD/2 could be transmitted to output directly for logic ‘1’ to eliminate direct current from source to ground. This is provided by proper division of truth table and using two level output gates. Also for extending to multi bit multiplier in this way, three type of half adders and one full adder are designed using two supply voltages and removing direct current. The implementation for two bits is reported. The results of simulation, using Hspice software and Stanford 32 nm CNTFET library with the voltage of 0.9 (v), as expected, indicate much lower power dissipation and power delay product (PDP) in comparison with the previous works.

[1]  Hakan Kuntman,et al.  A New Low Distortion Analog Multiplier , 2003 .

[2]  Fabrizio Lombardi,et al.  Device Model for Ballistic CNFETs Using the First Conducting Band , 2008, IEEE Design & Test of Computers.

[3]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[4]  J. Knoch,et al.  High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.

[5]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[6]  Mark S. Lundstrom,et al.  Theory of ballistic nanotransistors , 2003 .

[7]  Andreas Antoniou,et al.  Low power dissipation MOS ternary logic family , 1984 .

[8]  K. Sridharan,et al.  Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Keivan Navi,et al.  Design of energy-efficient and robust ternary circuits for nanotechnology , 2011, IET Circuits Devices Syst..

[10]  Jörg Appenzeller,et al.  Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.

[11]  Keivan Navi,et al.  Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics , 2011 .

[12]  Masao Mukaidono.  Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity , 1986, IEEE Transactions on Computers.

[13]  Balwinder Raj,et al.  Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM , 2017 .

[14]  Yong-Bin Kim,et al.  CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.

[15]  H. T. Mouftah,et al.  Depletion/enhancement CMOS for a lower power family of three-valued logic circuits , 1985 .

[16]  N. Goldsman,et al.  Electron Transport and Velocity Oscillations in a Carbon Nanotube , 2007, IEEE Transactions on Nanotechnology.

[17]  K. Sridharan,et al.  Efficient Multiternary Digit Adder Design in CNTFET Technology , 2013, IEEE Transactions on Nanotechnology.