Field programmable port extender (FPX) for distributed routing and queuing

Field Programmable Gate Arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the Field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic. FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports. Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be reprogrammed dynamically via control cells sent over the network. The flexibility of the FPX has made the card of interest for several networking applications. This year, fifty FPX hardware modules will be fabricated and distributed to researchers at eight universities around the country who are interested in experimenting with reprogrammable networks and per-flow queuing mechanisms. The FPX hardware will first be used to implement fast IP lookup algorithms and distributed input queueing.

[1]  Jonathan S. Turner,et al.  Design of a gigabit ATM switch , 1997, Proceedings of INFOCOM '97.

[2]  Sung-Mo Kang,et al.  A high-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches , 1997, Proceedings of INFOCOM '97.

[3]  John W. Lockwood,et al.  FPGA prototype queuing module for high performance ATM switching , 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

[4]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[5]  Will Eatherton.  Hardware-based internet protocol prefix lookups , 1998 .

[6]  M. J. Karol,et al.  Queueing in space-division packet switching , 1988, IEEE INFOCOM '88,Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?.

[7]  Sung-Mo Kang,et al.  Matrix unit cell scheduler (MUCS) for input-buffered ATM switches , 1998, IEEE Communications Letters.

[8]  Jean C. Walrand,et al.  Achieving 100% throughput in an input-queued switch , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[9]  Sung-Mo Kang,et al.  Scalable optoelectronic ATM networks: the iPOINT fully functional testbed , 1995 .

[10]  Nick McKeown,et al.  A practical scheduling algorithm to achieve 100% throughput in input-queued switches , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[11]  Bernhard Plattner,et al.  Scalable high speed IP routing lookups , 1997, SIGCOMM '97.

[12]  Nick McKeown,et al.  The Tiny Tera: A Packet Switch Core , 1998, IEEE Micro.