Comparative Study of HC-Degradation of NMOS and PMOS Devices with n+ and p+ Gate: Experiments and Simulation

A comparative .study of hot-carrier degraded NMOS and PMOS devices with either n' or p' gates is presented. Utilizing our new simulation tool, w€ have performed a very detailed analysis of the experimental results. To simulate hot-carrier degradation we have extended MINIMOS in a way which allows to directly monitor the build up of charge and interface states during the DC stress experiment. The direct comparison of experimental and simulation resuLts provides new insights in the physics ,of hot-carrier degradation of advanced submicron CMOS devices with ,rr and p+ gate material. c-6-5