Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs

This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection as delay faults of bridging faults in BiCMOS circuits is more difficult than in the CMOS case.<<ETX>>

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