Metal gates for advanced sub-80-nm SOI CMOS technology

Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-80-nm PD and FD SOI device performance. The optimal gate workfunction for the 50 nm technology node is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS). Midgap gates are not suitable for PD SOI CMOS due to the severe short-channel effects, but are desirable for FD SOI CMOS.