MBIST for LEON3 processor core cache
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The paper presents a testing method for cache memories of specific processor core. The proposed method uses specially designed scalable MBIST architecture to perform all desired test operations and is independent of memory cache type. The designed MBIST architecture allows performing tests even during processor's functional mode which is the main advantage over software-based solutions. Achieved results are demonstrated by test execution time.
[1] Heinrich Theodor Vierhaus,et al. Design and Test Technology for Dependable Systems-on-Chip , 2010 .
[2] J. Sosnowski,et al. Improving Software Based Self - Testing for Cache Memories , 2007, 2007 2nd International Design and Test Workshop.
[3] A. Razak,et al. Modeling and simulation of finite state machine Memory Built-in Self Test architecture for embedded memories , 2007, 2007 Asia-Pacific Conference on Applied Electromagnetics.