A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

This work presents a low-cost wireless system design that serves as an interface to support the SoC with contactless testability feature. The communication hierarchy includes PHY, MAC, data exchange, and test wrapper functions. The wireless does not require external antennae and crystal reference, and therefore minimize the setup cost. The embedded all-digital timing generation achieves robust performance in the noisy environment. The whole wireless system occupies a small area. In a 0.18µm device-under-test, the active area of wireless front-end is 0.14mm2 and the gate count for digital processing is 112K. The maximum energy efficiency for uplink is 1.1nJ/bit and for downlink is 2.9nJ/bit when the wireless distance is set around 1cm. The prototype system includes test equipment and an SoC as the device-under-test. The SoC integrating logic, memory, and analog plug-in modules can be contactlessly tested. It is a low-cost platform controlled by a simple hand-held computer.

[1]  Yasuhiro Morita,et al.  An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing , 2010, IEEE Journal of Solid-State Circuits.

[2]  Shi-Yu Huang,et al.  A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Shi-Yu Huang,et al.  The HOY Tester-Can IC Testing Go Wireless? , 2006, 2006 International Symposium on VLSI Design, Automation and Test.

[4]  Ying-Yen Chen,et al.  Automatic Test Wrapper Synthesis for a Wireless ATE Platform , 2010, IEEE Design & Test of Computers.

[5]  Poras T. Balsara,et al.  Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  D. Ruffieux,et al.  A 1 V 433/868 MHz 25 kb/s-FSK 2 kb/s-OOK RF transceiver SoC in standard digital 0.18 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  Fredrik Jonsson,et al.  A Low-Leakage Open-Loop Frequency Synthesizer Allowing Small-Area On-Chip Loop Filter , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Tao Wang,et al.  A 0.5 V 3.1 mW Fully Monolithic OOK Receiver for Wireless Local Area Sensor Network , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[9]  Catherine Dehollain,et al.  A 2-V 600-/spl mu/A 1-GHz BiCMOS super-regenerative receiver for ISM applications , 1998 .

[10]  Martin Margala,et al.  Design of wireless on-wafer submicron characterization system , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Cheng-Wen Wu,et al.  Economic Analysis of the HOY Wireless Test Methodology , 2010, IEEE Design & Test of Computers.

[12]  K.S.J. Pister,et al.  Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply , 2006, IEEE Journal of Solid-State Circuits.

[13]  Lars C. Jansson,et al.  A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.