Adaptive delay bank filter for selective elimination of harmonics in SRF-PLL structures

This paper proposes the usage of adaptive delay bank (ADB) based on cascaded delayed signal cancellation (CDSC) structure for selective elimination of the harmonics in the synchronous reference frame phase locked loop (SRF-PLL) structures. The ADB is inserted inside the SRF-PLL structure and it is frequency adaptive, which is the advantage over CDSC structures which are used in PLL as pre-filters, not being adaptive at all. Detailed mathematical analysis and simulation results confirmed suggested method for selective harmonic elimination in PLL.

[1]  V. Blasko,et al.  Operation of a phase locked loop system under distorted utility conditions , 1997 .

[2]  Frede Blaabjerg,et al.  Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions , 2011, IEEE Transactions on Industrial Electronics.

[3]  J. Doval-Gandoy,et al.  Tuning of Phase-Locked Loops for Power Converters Under Distorted Utility Conditions , 2009, IEEE Transactions on Industry Applications.

[4]  Yun Wei Li,et al.  Grid synchronization PLL based on cascaded delayed signal cancellation , 2010, 2010 IEEE Energy Conversion Congress and Exposition.

[5]  Marco Liserre,et al.  New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions , 2006 .

[6]  Marcelo A. Pérez,et al.  A Robust Phase-Locked Loop Algorithm to Synchronize Static-Power Converters With Polluted AC Systems , 2008, IEEE Transactions on Industrial Electronics.

[7]  Alireza R. Bakhshai,et al.  Derivation and Design of In-Loop Filters in Phase-Locked Loop Systems , 2012, IEEE Transactions on Instrumentation and Measurement.

[8]  R. Bashirullah,et al.  A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters , 2007, IEEE Journal of Solid-State Circuits.

[9]  Se-Kyo Chung,et al.  A phase tracking system for three phase utility interface inverters , 2000 .

[10]  Alireza Bakhshai,et al.  Enhancing the three-phase synchronous reference frame PLL to remove unbalance and harmonic errors , 2009, 2009 35th Annual Conference of IEEE Industrial Electronics.

[11]  Francisco A. S. Neves,et al.  FPGA Implementation of the Generalized Delayed Signal Cancelation—Phase Locked Loop Method for Detecting Harmonic Sequence Components in Three-Phase Signals , 2013, IEEE Transactions on Industrial Electronics.

[12]  Slobodan Lubura,et al.  Single-phase phase locked loop with dc offset and noise rejection for photovoltaic inverters , 2014 .

[13]  Gabriel Garcerá,et al.  An Adaptive Synchronous-Reference-Frame Phase-Locked Loop for Power Quality Improvement in a Polluted Utility Grid , 2012, IEEE Transactions on Industrial Electronics.

[14]  Y. Li,et al.  Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL , 2011, IEEE Transactions on Power Electronics.