A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms)

A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calculates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node (“boot-strap effect”) has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-μm double-polysilicon double-metal nwell CMOS process, and the circuit operation has been experimentally verified. key words: νMOS, absolute value of di erence, Manhattan dis-

[1]  Tadashi Shibata,et al.  Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  Tadahiro Ohmi,et al.  Write/verify free analog non-volatile memory using a neuron-MOS comparator , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[3]  Allen Gersho,et al.  Vector quantization and signal compression , 1991, The Kluwer international series in engineering and computer science.

[4]  H. Onodera,et al.  A Memory-based Parallel Processor for Vector Quantization , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[5]  Tadashi Shibata,et al.  Neuron-MOS-based association hardware for real-time event recognition , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[6]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[7]  T. Ohmi,et al.  Advances in neuron-MOS applications , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  Tadashi Shibata,et al.  Neuron-MOS multiple-valued memory technology for intelligent data processing , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[9]  Tadashi Shibata,et al.  A neuron-MOS neural network using self-learning-compatible synapse circuits , 1995, IEEE J. Solid State Circuits.

[10]  Asad A. Abidi,et al.  An 8 b CMOS vector A/D converter , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  Tadashi Shibata,et al.  Neuron MOS winner-take-all circuit and its application to associative memory , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[12]  T. Morimoto,et al.  A fully-parallel vector quantization processor for real-time motion picture compression , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[13]  G. Cauwenberghs,et al.  A Charge-Based CMOS Parallel Analog Vector Quantizer , 1994, NIPS 1994.