Novel tri-independent-gate FinFET for multi-current modes control

Abstract In this paper, a novel tri-independent-gate (TIG) FinFET is presented for multi-current modes control for the first time. The entire integration flow of proposed TIG FinFET is fully compatible with the mainstream gate-first HKMG FinFET process. Five kinds of ON state modes and threshold voltages can be offered by TIG FinFET without additional voltage sources, and it is demonstrated to have a great potential in dynamic voltage SRAM design. The critical electrical parameters of TIG FinFET in different modes are fully investigated with TCAD simulation and compared to the traditional FinFET. TIG FinFET with double fins is found to possess a distinct different output and capacitance characteristics with single fin FinFET. The underlying physical mechanisms are analyzed and investigated in detail.

[1]  K. Roy,et al.  Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs , 2011, IEEE Transactions on Electron Devices.

[2]  Jaydeep P. Kulkarni,et al.  Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability , 2013, IEEE Transactions on Electron Devices.

[3]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[4]  Zhiyu Liu,et al.  Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability , 2007, 2007 Internatonal Conference on Microelectronics.

[5]  H. Yamauchi,et al.  A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel , 2004, IEEE Electron Device Letters.

[6]  C. Hu,et al.  A spacer patterning technology for nanoscale CMOS , 2002 .

[7]  H. Yamauchi,et al.  Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel , 2003, IEEE International Electron Devices Meeting 2003.

[8]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[9]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[10]  Z. Ren Nanoscale MOSFETS: Physics, Simulation and Design , 2006 .

[11]  E. Suzuki,et al.  Demonstration, analysis, and device design considerations for independent DG MOSFETs , 2005, IEEE Transactions on Electron Devices.

[12]  K. Roy,et al.  Technology and circuit design considerations in quasi-planar double-gate SRAM , 2006, IEEE Transactions on Electron Devices.

[13]  Zheng Guo,et al.  SRAM Read/Write Margin Enhancements Using FinFETs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.